How to efficiently invalidate cache?

Question about miss ratio with direct mapping cache and fully associative cache?

• So here are the details: -Consider two alternate caches, each with 4 sectors holding 1 block per sector and one 32-bit word per block. One cache is direct mapped and the other is fully associative with LRU replacement policy. The machine is byte addressed on word boundaries and uses write allocation with write back. The question im stuck on is : 3b). Give an example address stream consisting of only reads that would result in a lower miss ratio if fed to the direct mapped cache than if it were fed to the fully associative cache. Under the problem it has this writen: read 0x00 read 0x04 read 0x08 read 0x0C read 0x14 read 0x00 Any suggestions? I know that fully associative can place any block in main memory in any block in the cache and direct is based on the equation = (block addr. in mem) MOD (# of block frames in cache)

• Answer:

  read 0x14 ; victim 0x00 on associative but 0x04 on direct read 0x00 ; miss on associative, but hit on direct