What is really the difference between FPGA and ASIC?

Are there any research institutes or universities, that are extensively working on ASIC/FPGA verification (or related), where I can apply and do research?

• I am working as ASIC verification engineer, i have a plan to do MS/Phd in this field after 1/2 years.

• Answer:

  It depends on what do you mean by ASIC/FPGA/VLSI verification, henceforth denoted as VLSI verification. If you are concerned about the methodology, well, guess what? The verification methodology partially, if not mostly, depends on the availability and capabilities of the verification point tools. Hence, there is only so much work you can do with respect to VLSI verification methodology for a given set of verification tools. However, if you have a good background in electrical engineering (EE), based on the definition of the U.S.-based Accreditation Board for Engineering and Technology (ABET), and computer science (CS), you can choose to work on the VLSI verification tools and VLSI verification methodology. which can be modified by the tools that you develop. Note that the ABET definition contains a considerable amount of computer engineering, power engineering, control engineering, analog and mixed-signal IC design and testing, and other common EE research areas such as signal processing and telecommunications. If you do not have a strong EECS (EE + CS) background, developing decent VLSI verification tools can be very challenging. As we make a push for more mixed-signal SoCs, the demand for VLSI verification tools and methodologies to address mixed-signal VLSI systems will increase. This would go beyond traditional circuit simulation tools, and can be modified and extended for cyber-physical systems (which are hybrid systems, just like mixed-signal circuits). Some universities focus on the computational engines of the VLSI verification tools, such as the model checkers, equivalence checkers, and theorem provers. Examples of such computational engines are SAT solvers and SMT solvers. The University of Trento in Trento, Italy has a world-class team working on the MathSAT SMT solver. For VLSI formal verification, UC Berkeley's ABC tool is capable of sequential equivalence checking and sequential logic synthesis. VLSI/hardware model checking has a bunch of categories. So, I would look at the results of the hardware model checking competition. See http://fmv.jku.at/hwmcc12/results.html. As for hardware/VLSI theorem proving, it has yet to gain adequate traction/acceptance. There are some universities that work on semi-formal verification, particularly assertion-based VLSI verification. Generally, the tool development is not that fancy, except perhaps for assertion synthesis of industry-grade VLSI systems (hard to prove in academia). Personally, I would avoid this. For logic simulation, look at those that are based on parallel computing (i.e., based on GPGPU computing or many-core processors). University of Michigan was recently working on this. For circuit simulation, see UC Berkeley, UC Riverside, and University of Toronto. Also, pay attention to other forms of verification, such as timing verification (including SSTA, statistical static timing analysis) - University of Michigan, power verification (for power sign-off), DFM sign-off tools, thermal sign-off/analysis (UCSD, or UC San Diego), and what not.